C A P
Complexity Adaptive Processing

CAP Publications and Patents

Publications:

  • Energy Efficient Co-Adaptive Instruction Fetch and Issue, A. Buyuktosunoglu, T. Karkhanis, D.H. Albonesi, and P. Bose, 30th International Symposium on Computer Architecture, pp. 147-156, June 2003.

  • Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors, R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, 30th International Symposium on Computer Architecture, pp. 275-286, June 2003.

  • Profile-based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor, G. Magklis, M.L. Scott, G. Semeraro, D.H. Albonesi, and S. Dropsho, 30th International Symposium on Computer Architecture, pp. 14-25, June 2003.

  • B. D. Andreev, E. L. Titlebaum, and E. G. Friedman, "Orthogonal Code Generator for 3G Wireless Transceivers," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 229-232, April 2003.

  • M. A. El-Moursy and E. G. Friedman, "Shielding Effect of On-Chip Interconnect Inductance," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 165-170, April 2003.

  • M. A. El-Moursy and E. G. Friedman, "Optimum Wire Sizing of RLC Interconnect With Repeaters," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 27-32, April 2003.

  • V. Kursun and E. G. Friedman, "Monolithic DC-DC Converter Analysis and MOSFET Gate Voltage Optimization," Proceedings of the IEEE International Symposium on Quality Electronics Design Conference, pp. 279-284, March 2003.

  • D. Velenis, M. C. Papaefthymiou and E. G. Friedman, "Reduced Delay Uncertainty in High Performance Clock Distribution Networks," Proceedings of the Design Automation and Test in Europe (DATE) Conference, pp. 68-73, March 2003.

  • Front-End Policies for Improved Issue Efficiency in SMT Processors, A. El-Moursy and D.H. Albonesi, 9th International Symposium on High-Performance Computer Architecture, pp. 31-40, February 2003.

  • Dynamic Data Dependence Tracking and its Application to Branch Prediction, L. Chen, S. Dropsho, and D.H. Albonesi, 9th International Symposium on High-Performance Computer Architecture, pp. 65-76, February 2003.

  • M. A. El-Moursy and E. G. Friedman, "Optimizing Inductive Interconnect for Low Power," System-on-Chip for Real-Time Applications, W. Badawy and G. A. Jullien (Eds.), Norwell, Massachusetts:Kluwer Academic Publishers, Section 9.2, pp. 380-391, 2003, ISBN # 1-4020-7254-6.

  • A. V. Mezhiba and E. G. Friedman, "Inductive Properties of High-Performance Power Distribution Grids," IEEE Transactions on VLSI Systems, Vol. 10, No. 6, pp. 762-776, December 2002.

  • M. A. El-Moursy and E. G. Friedman, "Optimum Wire Sizing and Repeater Insertion in Distributed RLC Interconnect, Proceedings of the 26th Annual IEEE EDS/CAS Activities in Western New York Conference, p. 6, November 2002.

  • Dynamic Frequency and Voltage Control for a Multiple Clock Domain Microarchitecture, G. Semeraro, D.H. Albonesi, S.G. Dropsho, G. Magklis, S. Dwarkadas, and M.L. Scott, 35th International Symposium on Microarchitecture, pp. 356-367, November 2002.

  • Managing Static Leakage Energy in Microprocessor Functional Units, S. Dropsho, V. Kursun, D.H. Albonesi, S. Dwarkadas, and E.G. Friedman, 35th International Symposium on Microarchitecture, pp. 321-332, November 2002.

  • Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power, S. Dropsho, A. Buyuktosunoglu, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, G. Semeraro, G. Magklis, and M.L. Scott, 11th International Conference on Parallel Architectures and Compilation Techniques, pp. 141-152, September 2002.

  • V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, "Efficiency Analysis of a High Frequency Buck Converter for On-Chip Integration with a Dual-VDD Microprocessor," Proceedings of the European Solid-State Circuit Conference, pp. 743-746, September 2002.

  • V. Kursun and E G. Friedman, "Domino Logic with Dynamic Body Biased Keeper," Proceedings of the European Solid-State Circuit Conference, pp. 675-678, September 2002.

  • V. Kursun and E. G. Friedman, "Variable Threshold Voltage Keeper for Contention Reduction in Dynamic Circuits," Proceedings of the IEEE International ASIC/SOC Conference, pp. 314-318, September 2002.

  • A. V. Mezhiba and E. G. Friedman, "Variation of Inductance with Frequency in High Performance Power Distribution Grids," Proceedings of the IEEE International ASIC/SOC Conference, pp. 421-425, September 2002.

  • An Oldest-First Selection Logic Implementation for Non-Compacting Issue Queues, A. Buyuktosunoglu, A. El-Moursy, and D.H. Albonesi, 15th International ASIC/SOC Conference, pp. 31-35, September 2002.

  • Tradeoffs in Power-Efficient Issue Queue Design, A. Buyuktosunoglu, D.H. Albonesi, P. Bose, P. Cook, S. Schuster, International Symposium on Low Power Electronics and Design, pp. 184-189, August 2002.

  • A Microarchitectural-Level Step-Power Analysis Tool, W. El-Essawy, D.H. Albonesi, and B. Sinharoy, International Symposium on Low Power Electronics and Design, pp. 263-266, August 2002.

  • K. T. Tang and E. G. Friedman, "Simultaneous Switching Noise in On-Chip CMOS Power Distribution Networks," IEEE Transactions on VLSI Systems, Vol. 10, No. 4, pp. 487-493, August 2002.

  • Y. I. Ismail and E. G. Friedman, "Inductance Effects in RLC Trees," Journal of Circuits, Systems and Computers, Vol. 11, No. 3, pp. 305-321, June 2002.

  • D. Velenis, K. T. Tang, I. S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, "Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling," Journal of Circuits, Systems and Computers, Vol. 11, No. 3, pp. 231-245, June 2002.

  • V. Kursun, R. M. Secareanu, and E. G. Friedman, "CMOS Voltage Interface Circuit for Low Power Systems," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3.667-3.670, May 2002.

  • A. V. Mezhiba and E. G. Friedman, "Inductance/Area/Resistance Tradeoffs in High Performance Power Distribution Grids," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.101-1.104, May 2002.

  • V. Kursun and E. G. Friedman, "Low Swing Dual Threshold Voltage Domino Logic," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 47-52, April 2002.

  • A. V. Mezhiba and E. G. Friedman, "Properties of On-Chip Inductive Current Loops," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 12-17, April 2002.

  • A. V. Mezhiba and E. G. Friedman, "Scaling Trends of On-Chip Power Distribution Noise," Proceedings of the IEEE International Workshop on System-Level Interconnect Prediction Conference, pp. 47-53, April 2002.

  • A. V. Mezhiba and E. G. Friedman, "Inductive Properties of Power Distribution Grids in High Speed Integrated Circuits," Proceedings of the IEEE International Symposium on Quality Electronics Design Conference, pp. 316-321, March 2002.

  • Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling , G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M.L. Scott, 8th International Symposium on High-Performance Computer Architecture, pp. 29-40, February 2002.

  • Early Stage Definition of LPX: A Low Power Issue-Execute Processor , P. Bose, D. Brooks, A. Buyuktosunoglu, P. Cook, K. Das, P. Emma, M. Gschwind, H. Jacobson, T. Karkhanis, P. Kudva, S. Schuster, J. Smith, V. Srinivasan, V. Zyuban, D. Albonesi, S. Dwarkadas, Workshop on Power-Aware Computer Systems, held at the 8th International Symposium on High-Performance Computer Architecture, February 2002.

  • Power-Efficient Issue Queue Design, A. Buyuktosunoglu, D.H. Albonesi, S. Schuster, D. Brooks, P. Bose, P. Cook, in Power Aware Computing, R. Graybill and R. Melhem (Eds), Kluwer Academic Publishers, Chapter 3, pp. 37-60, 2002.

  • A. V. Mezhiba and E. G. Friedman, "Tradeoffs in CMOS VLSI Circuits," Tradeoffs in Analog Circuits, Toumazou, Moshytz, and Gilbert (Eds.), Norwell, Massachusetts:Kluwer Academic Publishers, Chapter 3, pp. 75-114, 2002.

  • Low-Voltage 0.25um CMOS Improved Power Adaptive Issue Queue For Embedded Microprocessors, B. Curran, M. Gifaldi, J. Martin, A. Buyuktosunoglu, M. Margala, D. Albonesi, in SOC Design Methodologies, M. Robert, B. Rouzeyre, C. Piguet, and M.-L. Flottes (Eds), Kluwer Academic Publishers, pp. 289-300, 2002. (Selected paper from the 11th International Conference on VLSI-SOC, December 2001.)

  • Reducing the Complexity of the Register File in Dynamic Superscalar Processors , R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, 34th International Symposium on Microarchitecture, pp. 237-248, December 2001.

  • Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 963-973, December 2001.

  • V. Kursun, R. M. Secareanu, and E. G. Friedman, "Low Power CMOS Bi-Directional Voltage Converter," Proceedings of the 25rd Annual IEEE EDS/CAS Activities in Western New York Conference, pp. 6-7, November 2001.

  • D. Velenis, K. T. Tang, I. S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, "Demonstration of Power Enhancements on an Industrial Circuit Through Delay Management of Non-Critical Data Paths," Proceedings of the IEEE ASIC Conference, pp. 30-33, September 2001.

  • A Dynamic Reconfigurable Clock Generator , R.M. Secareanu, D. Albonesi, and E.G. Friedman, 14th International ASIC/SOC Conference, pp. 330-333, September 2001.

  • Dynamically Allocating Processor Resources Between Nearby and Distant ILP , R. Balasubramonian, S. Dwarkadas, and D.H. Albonesi, 28th International Symposium on Computer Architecture, pp. 26-37, June 2001.

  • R. M. Secareanu and E. G. Friedman, "Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity," Analog Integrated Circuits and Signal Processing, Volume 27, Number 3, pp. 275-279, June 2001.

  • Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Repeater Insertion in Tree Structured Inductive Interconnect," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 48, No. 5, pp. 471-481, May 2001.

  • E. G. Friedman, (Invited paper) " Clock Distribution Networks in Synchronous Digital Integrated Circuits," Proceedings of the IEEE, Vol. 89, No. 5, pp. 665-692, May 2001.

  • A Circuit Level Implementation of an Adaptive Issue Queue for Power-Aware Microprocessors, A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H. Albonesi, 11th Great Lakes Symposium on VLSI, pp. 73-78, March 2001.

  • Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures , R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, 33rd International Symposium on Microarchitecture, pp. 245-257, December 2000.

  • An Adaptive Issue Queue for Reduced Power at High Performance, A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H. Albonesi, Workshop on Power-Aware Computer Systems, held at the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, November 2000. Also appears in Springer-Verlag Lecture Notes in Computer Science, Volume 2008

  • Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 643-652, October 2000.

  • Dynamic Memory Hierarchy Performance Optimization, R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, Workshop on Solving the Memory Wall Problem, held at the 27th International Symposium on Computer Architecture, June 2000.

  • Selective Cache Ways: On-Demand Cache Resource Allocation, D.H. Albonesi, Journal of Instruction-Level Parallelism, Vol. 2, 2000.

  • Runtime Reconfiguration Techniques for Efficient General Purpose Computation, B. Xu and D.H. Albonesi, IEEE Design & Test of Computers, Special Issue on Configurable Computing, pp. 42-52, January-March 2000. Extended version

  • An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures, D.H. Albonesi, 10th International Conference on VLSI (VLSI'99), pp. 192-205, December 1999.

  • Selective Cache Ways: On-Demand Cache Resource Allocation, D.H. Albonesi, 32nd International Symposium on Microarchitecture (MICRO-32), pp. 248-259, November 1999.

  • A Methodology for the Analysis of Dynamic Application Parallelism and Its Application to Reconfigurable Computing, B. Xu and D.H. Albonesi, SPIE International Conference on Reconfigurable Technology: FPGAs for Computing and Applications, pp. 78-86, September 1999. Warning: Huge ps file

  • Dynamic IPC/Clock Rate Optimization, D.H. Albonesi, 25th International Symposium on Computer Architecture (ISCA'98), pp. 282-292, June 1998.

  • The Inherent Energy Efficiency of Complexity-Adaptive Processors, D.H. Albonesi, 1998 Power-Driven Microarchitecture Workshop, held at the 25th International Symposium on Computer Architecture, pp. 107-112, June 1998.

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    Patents (vastly outdated):

  • Mechanism for Dynamically Adapting the Complexity of a Microprocessor, D.H. Albonesi, U.S. Patent 6,205,537, issued March 20, 2001.
  • Dynamically Tunable Memory Hierarchy, R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, filed, November 2000 (pending).
  • Method of Adaptive Control and Resizing of Issue Queue Structures Within an Out-of-order Superscalar Processor for Reduced Power at High Performance, A. Buyuktosunoglu, S. Schuster, D. Brooks, P. Bose, P. Cook, and D.H. Albonesi, filed, October 2001 (pending).