C A P
CAP ApproachThe CAP approach is to incorporate novel, low-intrusive feedback and control mechanisms into conventional microprocessors, so as to retain their high clock rates and high functional density while better matching their hardware resources to varying application phase characteristics. A combination of hardware and system software controls each element of performance and dynamic power: hardware complexity (switched capacitance), latency, clock frequency, and supply voltage. These elements are manifested as dynamic hardware structures and fine-grained clock frequency and voltage control circuits, and are controlled so as to meet performance objectives in the most power-efficient manner possible.
The dynamic hardware structures of the CAP project exploit the characteristics of major microprocessor hardware structures. In the very-deep-submicrometer regime, large on-chip RAM and CAM-based structures require repeaters in their global wires in order to minimize propagation delay. These repeaters are converted into low-overhead switches that electrically isolate individual sections of the structure, thereby allowing sections to be almost instantaneously turned on or off. The resulting dynamic hardware structures can be reorganized (e.g., resized) on-the-fly to to match the different hardware requirements of different application phases.
As part of the CAP project, a Multiple Clock Domain (MCD) processor microarchitecture is being investigated. In MCD, the processor is split into multiple domains, within which the frequency and supply voltage can be independently scaled. Synchronization circuits assure reliable communication among domains. In this manner, those domains that are not a performance bottleneck for a particular application phase can be run at lower frequency and voltage, thereby saving energy with tolerable performance impact. This fine-grain voltage scaling approach is effective across a wide range of general-purpose and embedded applications, in contrast to the limited utility of global voltage scaling.
Lower power organizational alternatives to complex hardware structures are also being developed as well as novel circuit and software techniques for power reduction.